In merging logic circuits and dynamic random access memory (DRAM) arrays on a single chip, compatibility is the primary issue with respect to both design and fabrication. Recently, with the continued decrease in device dimensions, it has become increasingly important to embedded DRAM technology. In semiconductor structure, DRAM capacitors have typically been either buried or stacked. Stacked capacitors can be either polycrystalline silicon (poly) or metal-insulator-metal (MIM). The MIM capacitors are embedded in the oxide layers above the active surface of the chip. Because the conductors of the interconnect layers are metal in construction, the capacitors formed between the interconnect layers are preferably of a metal-insulator-metal (MIM) construction to take advantage of processing steps and performance enhancements.
Recent research indicates that the electrical performance of MIM capacitors is strongly correlated with plasma-induced charge damage during deposition or etching process. This is particularly problematic with regard to plasma etching processes in back end of line (BEOL) wiring levels, which develop a high electric field across the top electrode and the bottom electrode of the MIM capacitor to force the charges through the metal lines and the underlying MIM capacitor, degrading the electrical performance and reliability of the MIM capacitor.
Accordingly, a protection methodology is needed to prevent plasma-induced charge damage generated in the fabrication of (BEOL) wiring levels of the MIM capacitor based memory device.